The present invention relates to a method of manufacturing semiconductor devices, and more particularly, to a trench isolation method of a semiconductor device.
An isolation process, which is an initial step in the manufacture of a semiconductor device, is very critical because it determines the size of an active region and a process margin for the following steps. As the level of integration of semiconductor devices increases, the size allowed for an isolation region reduces, to the point where a 64M DRAM requires a 0.26 .mu.m-technology and a 256M DRAM requires a 0.19 .mu.m-technology.
Recently, a trench isolation method has been widely used because it allows for isolation even in a small region. In a conventional trench isolation method, as shown in FIG. 1, a pad oxide layer pattern 15 and a nitride layer pattern 20, which define an active region 12, are formed on a semiconductor substrate 10. The nitride layer pattern 20 acts as a hard mask pattern during trench etching, and the pad oxide layer pattern 15 acts to relieve the transfer of stress between the nitride layer pattern 20 and the substrate 10.
The semiconductor substrate 10 is then etched to a predetermined depth using the nitride layer pattern 20 and the pad oxide layer pattern 15 as an etching mask, resulting in the formation of a trench 23. Subsequently, a thermal oxide layer 25 is formed on the side walls of the trench 23, and a nitride liner 30 is formed on the entire surface of the resultant structure such that it conforms to the shape of the resultant structure.
The thermal oxide layer 25 serves to aid in recovering from damage that may be caused to the substrate during the etching process for forming the trench 23. The nitride liner 30 is formed so as to relieve the stress that is applied to the substrate during the following thermal process. The trench 23 is then filled with an insulation layer 35.
Referring to FIG. 2, the insulation layer 35 is then planarized by taking the upper surface of the nitride layer pattern 20 as an end point for the planarization. Then, the nitride layer pattern 20 is removed, to expose the pad oxide layer pattern 15 and to cause a trench isolation layer 35a to partially protrude above the surface of the pad oxide layer pattern 15.
In the step of removing the nitride layer pattern 20, a phosphoric acid solution is generally used. Because the nitride liner 30 is directly connected to the nitride layer pattern 20, the phosphoric acid solution, which is an etchant, can also flow through the nitride liner 30, so that the nitride liner 30 will be etched together with the nitride layer pattern 20. In addition, the nitride layer pattern 20 is generally over-etched by about 30-40% to ensure complete removal of the nitride layer pattern 20. As a result, the nitride liner 30 is etched to a point below the upper surface of the substrate 10, resulting in a first dent A between the active region 12 and the trench isolation layer 35a.
Referring to FIG. 3, trench isolation is completed by removing the pad oxide layer pattern 15. To accomplish this, the isolation layer 35a is generally etched to a predetermined depth, resulting in a modified isolation layer 35b having a height that is nearly equal to the height of the substrate 10. During this process, the entire pad oxide layer pattern 15 and a part of the isolation layer 35a are removed, forming a second dent B having a width that is wider than that of the first dent A of FIG. 2.
When the second dent B is formed, it is filled with polysilicon, which is used to form a gate, and the polysilicon remains without being removed when the gate is formed on the active region 12. As a result, the active region 12 is surrounded by the polysilicon used to form the gate, thereby concentrating an electric field on the edge of the trench isolation region. Because of this, the threshold voltage of a transistor formed on the substrate will drop. Furthermore, if the transistor has a threshold voltage that is lower than an appropriate level, the transistor can operate incorrectly at a low voltage that is not greater than an operating voltage. In addition, electric charges stored in a capacitor can be lost, and such loss of electric charge can mean the loss of data in a memory cell. Therefore, a frequent refresh operation is required, to prevent the loss of data by compensating for the lost electric charges at a predetermined interval.
Furthermore, the pad oxide layer pattern 15 and the nitride layer pattern 20, which are shown in FIG. 1, are created by forming a pad oxide layer, a nitride layer, an anti-reflection layer, and a photoresist pattern on the substrate 10 in sequence, and by etching the anti-reflection layer, the nitride layer, and the pad oxide layer in sequence using the photoresist pattern as an etching mask. After removing the photoresist pattern, the trench 23 is formed using the pad oxide layer pattern 15, the nitride layer pattern 20 and an anti-reflection layer pattern (not shown) as an etching mask.
Then, a cleaning process is performed to remove contaminants generated during the etching process. In the cleaning process, the resultant structure is processed with a mixed solution of ammonium hydroxide, hydrogen peroxide, and water (standard cleaning solution-1 (SC-1)) and then a dilute hydrogen fluoride (HF) solution. However, during such a cleaning process, water spots can be generated by the reaction between the cleaning solutions and the anti-reflection layer.